Over the past few years, packaging of semiconductor integrated circuits utilizing chip carriers bonded to film circuits and/or to printed wiring boards (PWB) has become a major area of research and development (see, for example, the article by P. R. Jones entitled "Leadless Carriers, Components Increase Board Density by 6:1" in Electronics, Aug. 25, 1981, pages 137 to 140). When attaching leadless components and leadless chip carriers (LCC) to film circuits or printed wiring boards by means of soldering techniques, care should be taken to provide a spacing between the component/LCC and the film circuit or the PWB. Such spacing is required to enable the cleaning of the area underneath the component/LCC and to protect the circuitry under the LCC and on the PWB. Moreover, the LCC and the PWB often exhibit different thermal characteristics leading to in-plane stresses therebetween as the result of thermal mismatch. Also, any flexures of the film circuit or the PWB result in out-of-plane stresses on the leads connecting the LCC to the film circuit or the board. Prior art techniques have used small solder spheres or solder paste to attach LCC' s to substrates. Although such known techniques have been used for surface mounting of electronic circuits on substrates, there exists a need for a compliant solder joint to compensate for large stresses resulting from thermal mismatches between the chip carrier and the board, as well as from board warpage and flexure.